In some conventional methods of line buffer system design, a plurality of line buffers may be used to store incoming horizontal lines of data which may have been scanned from a horizontal line in an image. At any point in time, data may be written to a single line buffer while being read from all of the line buffers. A fixed sequence may be utilized to determine to which line buffer incoming data is to be written from among the plurality of line buffers. When writing to a line buffer data from among a plurality of line buffers, an entire incoming horizontal line of data may be written to the line buffer. Then a second line buffer from among the plurality of line buffers may be selected and data from a second incoming horizontal line of data will be written to the second line buffer. This, in turn, may be followed with the selection of a third line buffer to which data from a third incoming horizontal line of data may be written. Subsequent incoming horizontal lines of data may be written in a similar manner.
FIG. 1A is a block diagram of a conventional line buffer system design. Referring to FIG. 1A, there is shown write control logic 10, line buffers 12, 14, and 16, read address logic 18, data rotation logic 20, write enable signals 22, 24, and 26, write data signal 28, write address signal 30, read address signal 32, read data signals 34, 36, and 38, and line output signals 40, 42, and 44.
The read address logic 18 may be adapted to generate read addresses to the plurality of line buffers. Circuitry which implements the read address logic may generate addresses independently from the circuitry which generates write addresses to the plurality of line buffers.
The write control logic 10 may be adapted to control the selection of which line buffer is to be written, from among the plurality of line buffers 12, 14, and 16. An embodiment of circuitry for write control logic 10 may comprise generation of the plurality of write enable signals 22, 24, and 26, in which a separate such signal may be generated for each of a plurality of line buffers. In FIG. 1A the write enable signal 22 is coupled to the line buffer 12, the write enable signal 24 is coupled to the line buffer 14, and the write enable signal 26 is coupled to the line buffer 16.
The line buffers 12, 14, and 16 may be adapted to store data received from an input write data signal 28 which is presented to the write data (write_data) input of the line buffer. The location to which the write data input is stored in the line buffer may be determined by the write address signal 30, which is presented to the write address (write_addr) input to the line buffer. The write enable signals 22, 24, and 26 from the write control logic 10, which are presented to the write enable (wen) inputs to the line buffers 12, 14, and 16, may enable data presented to the write data (write_data) input to be stored in the line buffer at a location according to the write address signal 30 which is presented to the write address (write_addr) input of the line buffers. The line buffers 12, 14, and 16 may also be adapted to output read data signals 34, 36, and 38 which are presented from the read data (read_data) output of the line buffers. The read data signals presented at the read data (read_data) outputs from the line buffers may represent the data which is stored at a location as specified by the read address signal 32, which is presented to the read address (read_addr) inputs to the line buffers.
The data rotation logic 20 may comprise suitable logic, circuitry, and/or code that may be adapted to take as input, the plurality of read data signals 34, 36, and 38, and rearrange their order in the plurality of line output signals 40, 42, and 44.
In operation, the write control logic 10 may utilize a write enable signal, to send a signal which enables incoming horizontal data to be written to the line buffer which is coupled to that write enable signal. Concurrently, the other write enable signals, from among the plurality of write enable signals, may be utilized to send a signal which disables incoming horizontal data to be written to each of a plurality of line buffers which is coupled to one of the write enable signals. For example, the sending of an enable signal on the write enable signal 22, may enable the writing of incoming horizontal data which is contained in the write data signal 28, to the line buffer 12. The simultaneous sending of a disable signal on the write enable signals 24 and 26, may disable the writing of incoming horizontal data which is contained in the write data signal 28 to the line buffers 14 and 16.
The conventional method of line buffer design may entail reorganization of data from the plurality of line buffers such that the most recently received horizontal line of data appears on a specific output signal, while a second most recently received horizontal line of data appears on another specific output signal, and so forth. This rearrangement of the order of output signals from the line buffers may be necessary to meet the requirements for the presentation of horizontal lines of data to subsystems which follow the line buffer system.
The output from the plurality of line buffers may comprise a plurality of input lines to a proceeding subsystem. A subsystem following the line buffer system may require that the most recently received horizontal line of data always appear on a specific output line, the next most recently received horizontal line of data always appear on another specific output line, and so forth, for each of the plurality of output lines which are going to a proceeding subsystem. Unfortunately, the actual writing of data to line buffers may be such that the most recently received horizontal line may be stored at a different line buffer with each incoming horizontal line of data. For example with reference to FIG. 1A, at a particular time instant, the line buffer 16 may store the most recently received horizontal line of data, the line buffer 14 may store the previously received line of horizontal data, and the line buffer 12 may store the line of horizontal data which arrived prior to the line of horizontal data stored in the line buffer 14.
After the line buffer 16 has completed receipt of the most recently received horizontal line of data, the write control logic may enable the line buffer 12 to receive the next incoming line of horizontal data. At a subsequent time instant, that next incoming line of horizontal data may have been stored at the line buffer 12. This may indicate that the line buffer 12 now stores the most recently received horizontal line of data, the line buffer 16 may store the previously received line of horizontal data, while the line buffer 14 may store the horizontal line of data which arrived prior to the horizontal line of data stored at line buffer 16.
The data rotation logic 20 may be adapted to receive, as an input, the output being read from each of the plurality of line buffers. Circuitry implementing the data rotation logic may then determine which of the line buffers contains the most recently received horizontal line of data, based upon the known fixed sequence in which line buffers are written. That data may them be transferred to a specific line output signal 40, 42, or 44 from the data rotation logic 20, which may be designated to always present the most recently received horizontal line of data to a proceeding subsystem. Similarly, the data rotation logic circuitry may also identify which line buffer contains the second most recently received horizontal line of data, and so forth.
For example, referring to FIG. 1A, the output signal 40 from data rotation logic 20, may be designated as the output which is to present the most recently received horizontal line of data, designated as line=K, where K represents an order in which the line arrived relative to other incoming lines of horizontal data. Furthermore, the output signal 42 may be designated to present the previously received horizontal line of data, designated as line=K−1, while the output signal 44 may be designated to present a horizontal line of data received prior to the horizontal line of data presented at the output 42, designated as line=K−2. When line buffer 12 stores the most recently received line of data, the output signal 34 may be coupled to the output signal 40 by the data rotation logic 20. When the line buffer 12 stores the previously received horizontal line of data, the output signal 34 may be coupled to output signal 42. When the line buffer 12 stores the line received prior to the previously received horizontal line of data, the output signal 34 may be coupled to the output signal 44.
When the line buffer 14 stores the most recently received line of data, the output signal 36 may be coupled to the output signal 40 by the data rotation logic 20. When the line buffer 14 stores the previously received horizontal line of data, output signal 36 may be coupled to the output signal 42. When the line buffer 14 stores the line that was received prior to the previously received horizontal line of data, the output signal 36 may be coupled to the output signal 44. When the line buffer 16 stores the most recently received line of data, the output signal 38 may be coupled to the output signal 40 by the data rotation logic 20. When line buffer 16 stores the previously received horizontal line of data, the output signal 38 may be coupled to the output signal 42. When the line buffer 16 stores the line that was received prior to the previously received horizontal line of data, the output signal 38 may be coupled to the output signal 44.
Some applications may discard bits which are contained in the data in some horizontal lines of data. However since, at some time, each line buffer may store a line from each ordinal position, most recently received line, second most recently received line, and so forth, from among the plurality of lines which may be stored simultaneously in the line buffer system design, all line buffers among the plurality of line buffers may be required to be of the same width.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.